1. Field of the Invention
The present invention relates to a method for forming a dummy pattern and, more particularly, to a method for forming a dummy pattern in a semiconductor device having a multilayer metallization structure.
2. Description of the Related Art
As the densities of LSIs are increased, more devices, especially conducting metallization, are formed as multilayer structures. Therefore, the absolute steps in devices between portions where conductive interconnect patterns exist and portions where no conductive interconnect pattern exist are increased with each year.
In order to photolithographically pattern metallizations located at different heights to form conductive interconnects, it is necessary to secure a margin for the depth of focus. However, the depth of focus and the resolution have a conflicting relationship and so limitations are imposed on thinning of conductive interconnects of multilayer metallization structure.
In an attempt to solve this problem, methods consisting of forming a dummy pattern in a location where no conductive interconnect pattern exists so as to make uniform absolute steps on devices have been proposed. Generally, two methods are known as these methods. In one method (1), if conductive interconnects run on a grid as in a gate array, a dummy pattern consisting of hatched portions in FIG. 1A is created on the grid G consisting of a pattern of small islands. In the other method (2), a dummy pattern indicated by the hatched portion in FIG. 1B is so formed that it covers the whole area where no conductive interconnects exist and that the dummy pattern is at some distance S from the conductive interconnect pattern.
However, the former method (1) is applied to patterns consisting of interconnects arranged regularly such as gate arrays. Therefore, this method cannot be applied to patterns consisting of conductive interconnects arranged irregularly. In the latter method (2), a conductive interconnect pattern of a large area exists and so stress is concentrated in the pattern, thus causing an explosion. Also, the capacitance between adjacent conductive interconnects increases, resulting in crosstalk between them.
Referring to FIG. 2, let I.sub.1, I.sub.2, . . . , I.sub.7 be Al interconnects. Let C.sub.0 be the capacitance of the bottoms of the interconnects. Let C.sub.1 be the capacitance of the side surfaces of the interconnects. The capacitance Ca between the adjacent interconnects I.sub.1 and I.sub.2 is given by Ca.noteq.C.sub.1 +C.sub.0 /2. The capacitance Cb between the adjacent conductive interconnects I.sub.1 and I.sub.7 is given by Cb.noteq.C.sub.0 /2. Thus, capacitances between conductive interconnects which are remote from each other such as between I.sub.1 and I.sub.7 cannot be neglected.
A combination of the methods (1) and (2) described above may be contemplated. In this case, arithmetic operations at the boundary between a dummy pattern and a conductive interconnect pattern are necessary. Also, it is necessary to perform a design rule check. In this way, the arithmetic operations performed during automatic pattern creation are too complex.
Where contact holes for connecting a conductive interconnect pattern on an upper layer with a conductive interconnect pattern on a lower layer are formed, an absolute step h is created across the interlayer film due to a device step formed by the presence and absence of conductive interconnect pattern, as shown in FIG. 3A. Therefore, if the depth of focus is varied and an exposure operation is performed when contact holes are created, the holes vary in diameter because the thickness of the photoresist is not uniform.
Depending on the process for flattening the interlayer film, the interlayer film in which contact holes are formed may have different thicknesses such as h.sub.1 and h.sub.2 in different locations, as shown in FIG. 3B.
In this case, the interlayer film having nonuniform thickness is subjected to reactive ion etching (RIE) and so contact holes formed in thin portions of the interlayer film are overetched. Consequently, the underlying aluminum layer is etched, and a compound of the aluminum and the photoresist adheres to the side wall of the photoresist. After removal of the photoresist, the compound is left behind, resulting in so-called crown. This will hinder burying the contact holes.